//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//   using 3Dmigoto v0.6.6 on Wed Jun 22 20:19:03 2022
//
//
// Buffer Definitions:
//
// cbuffer UnityPerDraw
// {
//
//   float4x4 glstate_matrix_mvp;       // Offset:    0 Size:    64
//   float4x4 glstate_matrix_modelview0;// Offset:   64 Size:    64 [unused]
//   float4x4 glstate_matrix_invtrans_modelview0;// Offset:  128 Size:    64 [unused]
//   float4x4 _Object2World;            // Offset:  192 Size:    64
//   float4x4 _World2Object;            // Offset:  256 Size:    64 [unused]
//   float4 unity_LODFade;              // Offset:  320 Size:    16 [unused]
//   float4 unity_WorldTransformParams; // Offset:  336 Size:    16 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// OutputInverseMVP                      UAV  float4         buf    0        1
// OutputInverseVP                       UAV  float4         buf    1        1
// UnityPerDraw                      cbuffer      NA          NA   11        1
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_0
dcl_globalFlags refactoringAllowed
dcl_immediateConstantBuffer { { 1.000000, 0, 0, 0},
                              { 0, 1.000000, 0, 0},
                              { 0, 0, 1.000000, 0},
                              { 0, 0, 0, 1.000000} }
dcl_constantbuffer CB11[16], immediateIndexed
dcl_uav_typed_buffer (float,float,float,float) u0
dcl_uav_typed_buffer (float,float,float,float) u1
dcl_input vThreadID.x
dcl_temps 7
dcl_tgsm_raw g0, 64
dcl_thread_group 4, 1, 1
and r0.x, vThreadID.x, l(1)
movc r0.x, r0.x, l(-1.000000), l(1.000000)
ult r0.yzw, vThreadID.xxxx, l(0, 1, 2, 3)
and r0.yzw, r0.yyzw, l(0, 1, 1, 1)
dp2 r1.x, cb11[1].yzyy, icb[r0.z + 0].xyxx
dp2 r1.w, cb11[2].yzyy, icb[r0.z + 0].xyxx
dp2 r1.z, cb11[0].yzyy, icb[r0.z + 0].xyxx
dp2 r1.y, cb11[3].yzyy, icb[r0.z + 0].xyxx
mul r2.xyzw, r0.xxxx, r1.xyzw
mul r3.xyzw, r0.xxxx, r1.ywyx
mul r1.xyzw, r0.xxxx, r1.yzyz
dp2 r4.y, cb11[3].zwzz, icb[r0.w + 0].xyxx
dp2 r4.z, cb11[0].zwzz, icb[r0.w + 0].xyxx
mul r5.xyzw, r2.xyzw, r4.yzyz
dp2 r4.x, cb11[1].zwzz, icb[r0.w + 0].xyxx
dp2 r4.w, cb11[2].zwzz, icb[r0.w + 0].xyxx
mad r1.xyzw, r1.xyzw, r4.xyzw, -r5.xyzw
dp2 r5.z, cb11[1].xyxx, icb[r0.y + 0].xyxx
dp2 r5.y, cb11[2].xyxx, icb[r0.y + 0].xyxx
mul r1.xyzw, r1.xyzw, r5.yyzz
mul r6.xyzw, r3.xyzw, r4.wyxw
mad r3.xyzw, r3.yzwy, r4.ywyx, -r6.xyzw
dp2 r5.w, cb11[0].xyxx, icb[r0.y + 0].xyxx
dp2 r5.x, cb11[3].xyxx, icb[r0.y + 0].xyxx
mad r0.xyzw, r5.zwww, r3.xyzw, r1.xyzw
mul r1.xyzw, r2.wzxz, r4.xwzx
mad r1.xyzw, r2.xwzx, r4.wzxz, -r1.xyzw
mad r0.xyzw, r5.xxxy, r1.xyzw, r0.xyzw
mul r1.xyz, cb11[2].wyzw, cb11[3].zwyz
mad r1.xyz, cb11[2].zwyz, cb11[3].wyzw, -r1.xyzx
dp3 r1.x, r1.xyzx, cb11[1].yzwy
mul r2.xyz, cb11[2].zwxz, cb11[3].wxzw
mad r2.xyz, cb11[2].wxzw, cb11[3].zwxz, -r2.xyzx
dp3 r1.y, r2.xyzx, cb11[1].xzwx
mul r2.xyz, cb11[2].wxyw, cb11[3].ywxy
mad r2.xyz, cb11[2].ywxy, cb11[3].wxyw, -r2.xyzx
dp3 r1.z, r2.xyzx, cb11[1].xywx
mul r2.xyz, cb11[2].yzxy, cb11[3].zxyz
mad r2.xyz, cb11[2].zxyz, cb11[3].yzxy, -r2.xyzx
dp3 r1.w, r2.xyzx, cb11[1].xyzx
dp4 r1.x, r1.xyzw, cb11[0].xyzw
div r0.xyzw, r0.xyzw, r1.xxxx
ishl r1.x, vThreadID.x, l(2)
store_raw g0.x, r1.x, r0.x
iadd r1.xyz, r1.xxxx, l(16, 32, 48, 0)
store_raw g0.x, r1.x, r0.y
store_raw g0.x, r1.y, r0.z
store_raw g0.x, r1.z, r0.w
store_uav_typed u0.xyzw, vThreadID.xxxx, r0.xyzw
sync_g_t
ld_raw r0.xyzw, l(48), g0.xyzw
ld_raw r1.xyzw, l(32), g0.xyzw
ld_raw r2.xyzw, l(16), g0.xyzw
ld_raw r3.xyzw, l(0), g0.xyzw
mul r4.xyzw, r2.yyyy, cb11[13].xyzw
mad r4.xyzw, cb11[12].xyzw, r3.yyyy, r4.xyzw
mad r4.xyzw, cb11[14].xyzw, r1.yyyy, r4.xyzw
mad r4.xyzw, cb11[15].xyzw, r0.yyyy, r4.xyzw
mul r5.xyzw, r2.xxxx, cb11[13].xyzw
mad r5.xyzw, cb11[12].xyzw, r3.xxxx, r5.xyzw
mad r5.xyzw, cb11[14].xyzw, r1.xxxx, r5.xyzw
mad r5.xyzw, cb11[15].xyzw, r0.xxxx, r5.xyzw
mov r0.x, vThreadID.x
mul r5.xyzw, r5.xyzw, icb[r0.x + 0].xxxx
mad r4.xyzw, icb[r0.x + 0].yyyy, r4.xyzw, r5.xyzw
mul r5.xyzw, r2.zzzz, cb11[13].xyzw
mul r2.xyzw, r2.wwww, cb11[13].xyzw
mad r2.xyzw, cb11[12].xyzw, r3.wwww, r2.xyzw
mad r3.xyzw, cb11[12].xyzw, r3.zzzz, r5.xyzw
mad r3.xyzw, cb11[14].xyzw, r1.zzzz, r3.xyzw
mad r1.xyzw, cb11[14].xyzw, r1.wwww, r2.xyzw
mad r1.xyzw, cb11[15].xyzw, r0.wwww, r1.xyzw
mad r2.xyzw, cb11[15].xyzw, r0.zzzz, r3.xyzw
mad r2.xyzw, icb[r0.x + 0].zzzz, r2.xyzw, r4.xyzw
mad r0.xyzw, icb[r0.x + 0].wwww, r1.xyzw, r2.xyzw
store_uav_typed u1.xyzw, vThreadID.xxxx, r0.xyzw
ret
// Approximately 77 instruction slots used
