// AUTOMATICALLY CONVERTED FROM SHADER FIXES 
//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//   using 3Dmigoto v0.6.6 on Wed Jun 22 20:19:08 2022
//
//
// Buffer Definitions:
//
// cbuffer cb1
// {
//
//   float4 cb1[4];                     // Offset:    0 Size:    64
//
// }
//
// cbuffer cb0
// {
//
//   float4 cb0[7];                     // Offset:    0 Size:   112
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// StereoParams                      texture  float4          2d  125        1
// cb0                               cbuffer      NA          NA    0        1
// cb1                               cbuffer      NA          NA    1        1
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION                 0   xyzw        0     NONE   float   xyzw
// COLOR                    0   xyzw        1     NONE   float   xyzw
// TEXCOORD                 0   xy          2     NONE   float   xy
//
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_POSITION              0   xyzw        0      POS   float   xyzw
// COLOR                    0   xyzw        1     NONE   float   xyzw
// TEXCOORD                 0   xy          2     NONE   float   xy
// P                        0   x           3  RTINDEX    uint   x
//
vs_4_0
dcl_output_siv o3.x, rendertarget_array_index
dcl_constantbuffer CB1[4], immediateIndexed
dcl_constantbuffer CB0[7], immediateIndexed
dcl_resource_buffer (float,float,float,float) t125
dcl_input v0.xyzw
dcl_input v1.xyzw
dcl_input v2.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xyzw
dcl_output o2.xy
dcl_temps 7
ld_indexable(buffer)(float,float,float,float) r6.xyzw, l(0, 0, 0, 0), t125.xyzw
mov o3.x, r6.z
mul r0.xyzw, v0.yyyy, cb1[1].xyzw
mad r0.xyzw, cb1[0].xyzw, v0.xxxx, r0.xyzw
mad r0.xyzw, cb1[2].xyzw, v0.zzzz, r0.xyzw
mad r0.xyzw, cb1[3].xyzw, v0.wwww, r0.xyzw
ld r1.xyzw, l(0, 0, 0, 0), t125.xyzw
add r1.z, r0.w, -r1.y
mad r2.x, r1.x, r1.z, r0.x
mov r2.yzw, r0.yyzw
div r3.xyzw, r2.xyzw, r2.wwww
mul r3.xyzw, r1.yyyy, r3.xyzw
ne r1.x, l(0.000000, 0.000000, 0.000000, 0.000000), r1.y
lt r1.y, l(0.000000), r2.w
and r1.x, r1.y, r1.x
movc r4.xyzw, r1.xxxx, r3.xyzw, r0.xyzw
mov o1.xyzw, v1.xyzw
mad o2.xy, v2.xyxx, cb0[6].xyxx, cb0[6].zwzz
add r5.x, -r6.y, r4.w
mul r5.y, r6.x, r6.w
mad r5.x, r5.x, r5.y, r4.x
ne r5.y, l(1.000000), r4.w
movc r4.x, r5.y, r5.x, r4.x
mov o0.xyzw, r4.xyzw
ret
// Approximately 17 instruction slots used
