// AUTOMATICALLY CONVERTED FROM SHADER FIXES 
//
// Generated by Microsoft (R) D3D Shader Disassembler
//
//   using 3Dmigoto v0.6.6 on Wed Jun 22 20:18:14 2022
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_POSITION              0   xyzw        0      POS   float
// TEXCOORD                 0   xyzw        1     NONE   float   xy
// TEXCOORD                 1   xyzw        2     NONE   float   xyzw
//
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Target                0   xyzw        0   TARGET   float   xyzw
//
ps_4_0
dcl_constantbuffer CB0[30], immediateIndexed
dcl_constantbuffer CB1[9], immediateIndexed
dcl_sampler s0, mode_default
dcl_sampler s1, mode_default
dcl_sampler s2, mode_default
dcl_resource_texture2d (float,float,float,float) t0
dcl_resource_texture2d (float,float,float,float) t1
dcl_resource_texture2d (float,float,float,float) t2
dcl_input_ps linear v1.xy
dcl_input_ps linear v2.xyzw
dcl_output o0.xyzw
dcl_temps 5
dcl_constantbuffer CB10[4], immediateIndexed
dcl_resource_buffer (float,float,float,float) t125
ld_indexable(buffer)(float,float,float,float) r3.xyzw, l(0, 0, 0, 0), t125.xyzw
mul r3.w, -r3.x, r3.y
mad r4.xyz, -r3.wwww, cb10[0].xyzw, cb1[4].xyzw
mov_sat r0.xy, v1.yxyy
add r0.xy, r0.xyxx, -cb0[21].yxyy
div_sat r0.xy, r0.xyxx, cb0[21].wzww
mul r0.zw, r0.xxxy, cb0[7].yyyy
add r1.x, -cb0[7].y, l(1.000000)
mad r0.xy, r0.yxyy, r1.xxxx, r0.zwzz
mad r0.xy, r0.xyxx, cb0[20].zwzz, cb0[20].xyxx
sample r0.xyzw, r0.xyxx, t0.xyzw, s0
dp4_sat r1.x, r0.xyzw, cb0[8].xyzw
mad r0.xyzw, r1.xxxx, cb0[9].xyzw, r0.xyzw
div r0.xyz, r0.xyzx, r0.wwww
mul r0.xyzw, r0.xyzw, cb0[22].xyzw
add r0.xyzw, r0.xyzw, r0.xyzw
sample r1.xyzw, v2.xyxx, t1.xyzw, s1
mul r1.xyz, r0.xyzx, r1.xyzx
mul r1.xyz, r1.xyzx, cb0[29].xyzx
mad r1.xyz, r1.xyzx, l(10.000000, 10.000000, 10.000000, 0.000000), -r0.xyzx
add r2.xy, -cb0[28].zwzz, r4.xyxx
mad r2.xy, r2.xyxx, cb0[28].xxxx, v2.zwzz
sample r2.xyzw, r2.xyxx, t2.xyzw, s2
mul r1.w, r2.w, cb0[29].w
mad o0.xyz, r1.wwww, r1.xyzx, r0.xyzx
mov o0.w, r0.w
ret
// Approximately 0 instruction slots used
