// AUTOMATICALLY CONVERTED FROM SHADER FIXES 
//
// Generated by Microsoft (R) D3D Shader Disassembler
//
//   using 3Dmigoto v0.6.181 on Sat Aug 23 18:05:40 2025
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION                 0   xyz         0     NONE   float   xyz
// COLOR                    0   xyzw        1     NONE   float   xyzw
// TEXCOORD                 0   xy          2     NONE   float   xy
//
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position              0   xyzw        0      POS   float   xyzw
// TEXCOORD                 0   xyzw        1     NONE   float   xyzw
// TEXCOORD                 1   xy          2     NONE   float   xy
// TEXCOORD                 2   xyzw        3     NONE   float   xyzw
// TEXCOORD                 3   xyz         4     NONE   float   xyz
// P                        0   x           5  RTINDEX    uint   x
//
vs_5_0
dcl_output_siv o5.x, rendertarget_array_index
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[8], immediateIndexed
dcl_input v0.xyz
dcl_input v1.xyzw
dcl_input v2.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xyzw
dcl_output o2.xy
dcl_output o3.xyzw
dcl_output o4.xyz
dcl_temps 34
dcl_resource_buffer (float,float,float,float) t125
ld_indexable(buffer)(float,float,float,float) r33.xyzw, l(0, 0, 0, 0), t125.xyzw
mov o5.x, r33.z
ld_indexable(buffer)(float,float,float,float) r25.xyzw, l(0, 0, 0, 0), t125.xyzw
mul r0.xyzw, v0.yyyy, cb0[1].xyzw
mad r0.xyzw, cb0[0].xyzw, v0.xxxx, r0.xyzw
mad r0.xyzw, cb0[2].xyzw, v0.zzzz, r0.xyzw
add r10.xyzw, r0.xyzw, cb0[3].xyzw
eq r20.x, r10.w, l(1.000000)
if_nz r20.x
  mov r10.xyzw, l(0)
endif
mov r31.xyzw, r10.xyzw
mov o1.xyzw, v1.xyzw
mov o2.xy, v2.xyxx
mul r0.xyzw, v0.yyyy, cb0[5].xyzw
mad r0.xyzw, cb0[4].xyzw, v0.xxxx, r0.xyzw
mad r0.xyzw, cb0[6].xyzw, v0.zzzz, r0.xyzw
add o3.xyzw, r0.xyzw, cb0[7].xyzw
mov o4.xyz, v0.xyzx
add r32.x, -r33.y, r31.w
mul r32.y, r33.x, r33.w
mad r32.x, r32.x, r32.y, r31.x
ne r32.y, l(1.000000), r31.w
movc r31.x, r32.y, r32.x, r31.x
mov o0.xyzw, r31.xyzw
ret
// Approximately 0 instruction slots used
