//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//   using 3Dmigoto v0.6.181 on Sun Aug 27 22:06:13 2023
//
//
// Buffer Definitions:
//
// cbuffer GTAOConstantBuffer
// {
//
//   struct GTAOConstants
//   {
//
//       int2 ViewportSize;             // Index:    0
//       float2 ViewportPixelSize;      // Index:    0.z
//       float2 DepthUnpackConsts;      // Index:    1
//       float2 CameraTanHalfFOV;       // Index:    1.z
//       float2 NDCToViewMul;           // Index:    2
//       float2 NDCToViewAdd;           // Index:    2.z
//       float2 NDCToViewMul_x_PixelSize;// Index:    3
//       float EffectRadius;            // Index:    3.z
//       float EffectFalloffRange;      // Index:    3.w
//       float RadiusMultiplier;        // Index:    4
//       float Padding0;                // Index:    4.y
//       float FinalValuePower;         // Index:    4.z
//       float DenoiseBlurBeta;         // Index:    4.w
//       float SampleDistributionPower; // Index:    5
//       float ThinOccluderCompensation;// Index:    5.y
//       float DepthMIPSamplingOffset;  // Index:    5.z
//       int NoiseIndex;                // Index:    5.w
//
//   } g_GTAOConsts;                    // Index:    0-5              Components:    24
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// g_samplerPointClamp               sampler      NA          NA   10        1
// g_srcRawDepth                     texture   float          2d    0        1
// g_outWorkingDepthMIP0                 UAV   float          2d    0        1
// g_outWorkingDepthMIP1                 UAV   float          2d    1        1
// g_outWorkingDepthMIP2                 UAV   float          2d    2        1
// g_outWorkingDepthMIP3                 UAV   float          2d    3        1
// g_outWorkingDepthMIP4                 UAV   float          2d    4        1
// GTAOConstantBuffer                cbuffer      NA          NA    0        1
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_0
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[4], immediateIndexed
dcl_sampler s10, mode_default
dcl_resource_texture2d (float,float,float,float) t0
dcl_uav_typed_texture2d (float,float,float,float) u0
dcl_uav_typed_texture2d (float,float,float,float) u1
dcl_uav_typed_texture2d (float,float,float,float) u2
dcl_uav_typed_texture2d (float,float,float,float) u3
dcl_uav_typed_texture2d (float,float,float,float) u4
dcl_input vThreadIDInGroup.xy
dcl_input vThreadID.xy
dcl_temps 4
dcl_tgsm_structured g0, 32, 8
dcl_thread_group 8, 8, 1
ishl r0.xyzw, vThreadID.xyyy, l(1, 1, 1, 1)
utof r1.xy, r0.xwxx
mul r1.xy, r1.xyxx, cb0[0].zwzz
gather4_aoffimmi_indexable(1,1,0)(texture2d)(float,float,float,float) r1.xyzw, r1.xyxx, t0.xyzw, s10.x
add r1.xyzw, -r1.wzxy, cb0[1].yyyy
div r1.xyzw, cb0[1].xxxx, r1.xyzw
max r1.xyzw, r1.xyzw, l(0.000000, 0.000000, 0.000000, 0.000000)
min r1.xyzw, r1.xyzw, l(65504.000000, 65504.000000, 65504.000000, 65504.000000)
store_uav_typed u0.xyzw, r0.xyzw, r1.xxxx
imad r2.xyzw, vThreadID.xyxy, l(2, 2, 2, 2), l(1, 0, 0, 1)
store_uav_typed u0.xyzw, r2.xyyy, r1.yyyy
store_uav_typed u0.xyzw, r2.zwww, r1.zzzz
imad r2.xyzw, vThreadID.xyyy, l(2, 2, 2, 2), l(1, 1, 1, 1)
store_uav_typed u0.xyzw, r2.xyzw, r1.wwww
max r0.xy, r1.ywyy, r1.xzxx
max r0.x, r0.y, r0.x
mul r0.yz, cb0[3].zzzz, l(0.000000, 1.09275007, 0.672041297, 0.000000)
add r0.w, -cb0[3].w, l(1.000000)
mul r0.y, r0.w, r0.y
div r0.w, l(-1.000000), r0.z
div r0.y, r0.y, r0.z
add r0.y, r0.y, l(1.000000)
add r2.xyzw, -r1.xyzw, r0.xxxx
mad_sat r2.xyzw, r2.xyzw, r0.wwww, r0.yyyy
add r0.x, r2.y, r2.x
add r0.x, r2.z, r0.x
add r0.x, r2.w, r0.x
mul r1.xy, r1.xyxx, r2.xyxx
add r0.z, r1.y, r1.x
mad r0.z, r2.z, r1.z, r0.z
mad r0.z, r2.w, r1.w, r0.z
div r0.x, r0.z, r0.x
store_uav_typed u1.xyzw, vThreadID.xyyy, r0.xxxx
ishl r0.z, vThreadIDInGroup.y, l(2)
store_structured g0.x, vThreadIDInGroup.x, r0.z, r0.x
sync_g_t
and r1.xyzw, vThreadIDInGroup.xyxy, l(1, 1, 3, 3)
ieq r1.xyzw, r1.xyzw, l(0, 0, 0, 0)
and r1.xy, r1.ywyy, r1.xzxx
if_nz r1.x
  ld_structured r0.x, vThreadIDInGroup.x, r0.z, g0.xxxx
  iadd r1.x, vThreadIDInGroup.x, l(1)
  ld_structured r1.z, r1.x, r0.z, g0.xxxx
  iadd r1.w, r0.z, l(4)
  ld_structured r2.x, vThreadIDInGroup.x, r1.w, g0.xxxx
  ld_structured r1.x, r1.x, r1.w, g0.xxxx
  max r1.w, r0.x, r1.z
  max r2.y, r1.x, r2.x
  max r1.w, r1.w, r2.y
  add r2.y, -r0.x, r1.w
  mad_sat r2.y, r2.y, r0.w, r0.y
  add r2.z, -r1.z, r1.w
  mad_sat r2.z, r2.z, r0.w, r0.y
  add r2.w, -r2.x, r1.w
  mad_sat r2.w, r2.w, r0.w, r0.y
  add r1.w, -r1.x, r1.w
  mad_sat r1.w, r1.w, r0.w, r0.y
  add r3.x, r2.z, r2.y
  add r3.x, r2.w, r3.x
  add r3.x, r1.w, r3.x
  mul r1.z, r1.z, r2.z
  mad r0.x, r2.y, r0.x, r1.z
  mad r0.x, r2.w, r2.x, r0.x
  mad r0.x, r1.w, r1.x, r0.x
  div r0.x, r0.x, r3.x
  ushr r2.xyzw, vThreadID.xyyy, l(1, 1, 1, 1)
  store_uav_typed u2.xyzw, r2.xyzw, r0.xxxx
  store_structured g0.x, vThreadIDInGroup.x, r0.z, r0.x
endif
sync_g_t
if_nz r1.y
  ld_structured r0.x, vThreadIDInGroup.x, r0.z, g0.xxxx
  iadd r1.x, vThreadIDInGroup.x, l(2)
  ld_structured r1.y, r1.x, r0.z, g0.xxxx
  iadd r1.z, r0.z, l(8)
  ld_structured r1.w, vThreadIDInGroup.x, r1.z, g0.xxxx
  ld_structured r1.x, r1.x, r1.z, g0.xxxx
  max r1.z, r0.x, r1.y
  max r2.x, r1.x, r1.w
  max r1.z, r1.z, r2.x
  add r2.x, -r0.x, r1.z
  mad_sat r2.x, r2.x, r0.w, r0.y
  add r2.yz, -r1.yywy, r1.zzzz
  mad_sat r2.y, r2.y, r0.w, r0.y
  mad_sat r2.z, r2.z, r0.w, r0.y
  add r1.z, -r1.x, r1.z
  mad_sat r1.z, r1.z, r0.w, r0.y
  add r2.w, r2.y, r2.x
  add r2.w, r2.z, r2.w
  add r2.w, r1.z, r2.w
  mul r1.y, r1.y, r2.y
  mad r0.x, r2.x, r0.x, r1.y
  mad r0.x, r2.z, r1.w, r0.x
  mad r0.x, r1.z, r1.x, r0.x
  div r0.x, r0.x, r2.w
  ushr r1.xyzw, vThreadID.xyyy, l(2, 2, 2, 2)
  store_uav_typed u3.xyzw, r1.xyzw, r0.xxxx
  store_structured g0.x, vThreadIDInGroup.x, r0.z, r0.x
endif
sync_g_t
ieq r1.xy, vThreadIDInGroup.xyxx, l(0, 0, 0, 0)
and r0.x, r1.y, r1.x
if_nz r0.x
  ld_structured r0.x, vThreadIDInGroup.x, r0.z, g0.xxxx
  ld_structured r1.x, l(4), r0.z, g0.xxxx
  iadd r0.z, r0.z, l(16)
  ld_structured r1.y, vThreadIDInGroup.x, r0.z, g0.xxxx
  ld_structured r0.z, l(4), r0.z, g0.xxxx
  max r1.z, r0.x, r1.x
  max r1.w, r0.z, r1.y
  max r1.z, r1.w, r1.z
  add r1.w, -r0.x, r1.z
  mad_sat r1.w, r1.w, r0.w, r0.y
  add r2.xy, -r1.xyxx, r1.zzzz
  mad_sat r2.x, r2.x, r0.w, r0.y
  mad_sat r2.y, r2.y, r0.w, r0.y
  add r1.z, -r0.z, r1.z
  mad_sat r0.y, r1.z, r0.w, r0.y
  add r0.w, r1.w, r2.x
  add r0.w, r2.y, r0.w
  add r0.w, r0.y, r0.w
  mul r1.x, r1.x, r2.x
  mad r0.x, r1.w, r0.x, r1.x
  mad r0.x, r2.y, r1.y, r0.x
  mad r0.x, r0.y, r0.z, r0.x
  div r0.x, r0.x, r0.w
  ushr r1.xyzw, vThreadID.xyyy, l(3, 3, 3, 3)
  store_uav_typed u4.xyzw, r1.xyzw, r0.xxxx
endif
ret
// Approximately 130 instruction slots used
