// AUTOMATICALLY CONVERTED FROM SHADER FIXES 
//
// Generated by Microsoft (R) D3D Shader Disassembler
//
//   using 3Dmigoto v0.6.198 on Wed May 28 00:41:38 2025
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_0
dcl_constantbuffer CB12[2], immediateIndexed
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[1], immediateIndexed
dcl_sampler s0, mode_default
dcl_resource_texture2d (uint,uint,uint,uint) t0
dcl_uav_typed_texture2darray (uint,uint,uint,uint) u0
dcl_input vThreadID.xy
dcl_temps 5
dcl_thread_group 8, 8, 1
mov r5.z, l(0)
ishl r0.xy, vThreadID.xyxx, l(1, 1, 0, 0)
utof r0.xy, r0.xyxx
add r0.xy, r0.xyxx, l(0.500000, 0.500000, 0.000000, 0.000000)
mul r0.xy, r0.xyxx, cb0[0].xyxx
gather4_indexable(texture2d)(uint,uint,uint,uint) r0.xyzw, r0.xyxx, t0.xyzw, s0.x
and r1.xyzw, r0.xyzw, l(1023, 1023, 1023, 1023)
utof r1.xyzw, r1.zxwy
mov r2.xz, r1.yywy
ubfe r3.xyzw, l(10, 10, 10, 10), l(10, 10, 10, 10), r0.xyzw
utof r3.xyzw, r3.xyzw
mov r2.yw, r3.xxxy
mov r1.yw, r3.zzzw
mad r1.xyzw, r1.xyzw, l(0.00195503421, 0.00195503421, 0.00195503421, 0.00195503421), l(-1.000000, -1.000000, -1.000000, -1.000000)
mad r2.xyzw, r2.xyzw, l(0.00195503421, 0.00195503421, 0.00195503421, 0.00195503421), l(-1.000000, -1.000000, -1.000000, -1.000000)
add r3.xyzw, -|r2.yxwz|, l(1.000000, 1.000000, 1.000000, 1.000000)
ge r4.xyzw, r2.xyzw, l(0.000000, 0.000000, 0.000000, 0.000000)
movc r3.xyzw, r4.xyzw, r3.xyzw, -r3.xyzw
dp2 r4.x, l(1.000000, 1.000000, 0.000000, 0.000000), |r2.xyxx|
add r4.z, -r4.x, l(1.000000)
lt r4.w, r4.z, l(0.000000)
movc r4.xy, r4.wwww, r3.xyxx, r2.xyxx
dp3 r2.x, r4.xyzx, r4.xyzx
rsq r2.x, r2.x
mul r3.xy, r2.xxxx, r4.xyxx
mad r2.y, -r4.x, r2.x, -r3.y
mad r4.xy, r4.xyxx, r2.xxxx, -r3.yxyy
add r3.x, r3.y, r3.x
mad r3.x, r4.z, r2.x, r3.x
lt r3.x, l(0.000000), r3.x
movc r3.x, r3.x, l(64), l(128)
mad r4.xy, r4.zzzz, r2.xxxx, r4.xyxx
mad r2.x, r4.z, r2.x, r2.y
lt r2.x, l(0.000000), r2.x
movc r2.x, r2.x, l(1), l(2)
lt r4.xy, l(0.000000, 0.000000, 0.000000, 0.000000), r4.xyxx
movc r4.xy, r4.xyxx, l(4,16,0,0), l(8,32,0,0)
iadd r2.x, r2.x, r4.x
iadd r2.x, r2.x, r4.y
iadd r2.x, r2.x, r3.x
movc r0.x, r0.x, r2.x, l(0)
dp2 r2.x, l(1.000000, 1.000000, 0.000000, 0.000000), |r2.zwzz|
add r4.z, -r2.x, l(1.000000)
lt r2.x, r4.z, l(0.000000)
movc r4.xy, r2.xxxx, r3.zwzz, r2.zwzz
dp3 r2.x, r4.xyzx, r4.xyzx
rsq r2.x, r2.x
mul r2.yz, r2.xxxx, r4.xxyx
mad r2.w, -r4.x, r2.x, -r2.z
mad r3.xy, r4.xyxx, r2.xxxx, -r2.zyzz
add r2.y, r2.z, r2.y
mad r2.y, r4.z, r2.x, r2.y
lt r2.y, l(0.000000), r2.y
mad r3.xy, r4.zzzz, r2.xxxx, r3.xyxx
mad r2.x, r4.z, r2.x, r2.w
lt r2.x, l(0.000000), r2.x
lt r2.zw, l(0.000000, 0.000000, 0.000000, 0.000000), r3.xxxy
movc r2.xyzw, r2.xyzw, l(1,64,4,16), l(2,128,8,32)
iadd r2.x, r2.x, r2.z
iadd r2.x, r2.x, r2.w
iadd r2.x, r2.x, r2.y
movc r0.y, r0.y, r2.x, l(0)
or r0.x, r0.y, r0.x
add r2.xyzw, -|r1.yxwz|, l(1.000000, 1.000000, 1.000000, 1.000000)
ge r3.xyzw, r1.xyzw, l(0.000000, 0.000000, 0.000000, 0.000000)
movc r2.xyzw, r3.xyzw, r2.xyzw, -r2.xyzw
dp2 r0.y, l(1.000000, 1.000000, 0.000000, 0.000000), |r1.xyxx|
add r3.z, -r0.y, l(1.000000)
lt r0.y, r3.z, l(0.000000)
movc r3.xy, r0.yyyy, r2.xyxx, r1.xyxx
dp3 r0.y, r3.xyzx, r3.xyzx
rsq r0.y, r0.y
mul r1.xy, r0.yyyy, r3.xyxx
mad r2.x, -r3.x, r0.y, -r1.y
mad r3.xy, r3.xyxx, r0.yyyy, -r1.yxyy
add r1.x, r1.y, r1.x
mad r1.x, r3.z, r0.y, r1.x
lt r1.x, l(0.000000), r1.x
movc r1.x, r1.x, l(64), l(128)
mad r3.xy, r3.zzzz, r0.yyyy, r3.xyxx
mad r0.y, r3.z, r0.y, r2.x
lt r0.y, l(0.000000), r0.y
movc r0.y, r0.y, l(1), l(2)
lt r2.xy, l(0.000000, 0.000000, 0.000000, 0.000000), r3.xyxx
movc r2.xy, r2.xyxx, l(4,16,0,0), l(8,32,0,0)
iadd r0.y, r0.y, r2.x
iadd r0.y, r0.y, r2.y
iadd r0.y, r0.y, r1.x
movc r0.y, r0.z, r0.y, l(0)
or r0.x, r0.y, r0.x
dp2 r0.y, l(1.000000, 1.000000, 0.000000, 0.000000), |r1.zwzz|
add r3.z, -r0.y, l(1.000000)
lt r0.y, r3.z, l(0.000000)
movc r3.xy, r0.yyyy, r2.zwzz, r1.zwzz
dp3 r0.y, r3.xyzx, r3.xyzx
rsq r0.y, r0.y
mul r1.xy, r0.yyyy, r3.xyxx
mad r0.z, -r3.x, r0.y, -r1.y
mad r1.zw, r3.xxxy, r0.yyyy, -r1.yyyx
add r1.x, r1.y, r1.x
mad r1.x, r3.z, r0.y, r1.x
lt r1.x, l(0.000000), r1.x
mad r1.yz, r3.zzzz, r0.yyyy, r1.zzwz
mad r0.y, r3.z, r0.y, r0.z
lt r0.y, l(0.000000), r0.y
movc r0.y, r0.y, l(1), l(2)
lt r1.yz, l(0.000000, 0.000000, 0.000000, 0.000000), r1.yyzy
movc r1.xyz, r1.xyzx, l(64,4,16,0), l(128,8,32,0)
iadd r0.y, r0.y, r1.y
iadd r0.y, r0.y, r1.z
iadd r0.y, r0.y, r1.x
movc r0.y, r0.w, r0.y, l(0)
or r0.x, r0.y, r0.x
mov r5.xy, vThreadID.xyyy
store_uav_typed u0.xyzw, r5.xyzz, r0.xxxx
ret
// Approximately 0 instruction slots used
