// AUTOMATICALLY CONVERTED FROM SHADER FIXES 
//
// Generated by Microsoft (R) D3D Shader Disassembler
//
//   using 3Dmigoto v0.6.181 on Sat Dec 30 19:43:19 2023
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION                 0   xyzw        0     NONE   float   xyzw
// TEXCOORD                 4   xyzw        1     NONE   float   xyzw
// TEXCOORD                 5   xyzw        2     NONE   float   xyzw
// TEXCOORD                 6   xyzw        3     NONE   float   xyzw
//
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position              0   xyzw        0      POS   float   xyzw
// TEXCOORD                 0   xyzw        1     NONE   float   xyzw
// TEXCOORD                 1   xyzw        2     NONE   float   xyzw
// TEXCOORD                 2   xyz         3     NONE   float   xyz
// TEXCOORD                 3   xyzw        4     NONE   float   xyzw
// TEXCOORD                 4   xyzw        5     NONE   float   xyzw
// TEXCOORD                 5   xyzw        6     NONE   float   xyzw
// TEXCOORD                 6   xy          7     NONE   float   xy
// TEXCOORD                 7   xyzw        8     NONE   float   xyzw
// TEXCOORD                 8   xyzw        9     NONE   float   xyzw
// TEXCOORD                 9   xyzw       10     NONE   float   xyzw
// P                        0   x          11  RTINDEX    uint   x
//
vs_5_0
dcl_output_siv o11.x, rendertarget_array_index
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[6], immediateIndexed
dcl_constantbuffer CB2[17], immediateIndexed
dcl_constantbuffer CB12[3], immediateIndexed
dcl_input v0.xyzw
dcl_input v1.xyzw
dcl_input v2.xyzw
dcl_input v3.xyzw
dcl_output_siv o0.xyzw, position
dcl_output o1.xyzw
dcl_output o2.xyzw
dcl_output o3.xyz
dcl_output o4.xyzw
dcl_output o5.xyzw
dcl_output o6.xyzw
dcl_output o7.xy
dcl_output o8.xyzw
dcl_output o9.xyzw
dcl_output o10.xyzw
dcl_temps 18
dcl_resource_buffer (float,float,float,float) t125
ld_indexable(buffer)(float,float,float,float) r18.xyzw, l(0, 0, 0, 0), t125.xyzw
mov o11.x, r18.z
ld_indexable(buffer)(float,float,float,float) r4.xyzw, l(0, 0, 0, 0), t125.xyzw
mad r0.xyzw, v0.xyzw, l(8.000000, 8.000000, 8.000000, 8.000000), l(0.500000, 0.500000, 0.500000, 0.500000)
round_ni r0.xyzw, r0.xyzw
mul r0.xyzw, r0.xyzw, l(0.125000, 0.125000, 0.125000, 0.125000)
dp4 r1.y, r0.xyzw, v2.xyzw
dp4 r1.x, r0.xyzw, v1.xyzw
dp4 r1.z, r0.xyzw, v3.xyzw
mov o2.xyz, r0.xyzx
mov r1.w, l(1.000000)
dp4 r10.x, r1.xyzw, cb2[0].xyzw
dp4 r10.y, r1.xyzw, cb2[1].xyzw
dp4 r10.z, r1.xyzw, cb2[2].xyzw
dp4 r10.w, r1.xyzw, cb2[3].xyzw
ne r11.y, r10.w, l(1.000000)
if_nz r11.y
  add r11.x, r10.w, -r4.y
  mad r10.x, r4.x, r11.x, r10.x
endif
mov o0.xyzw, r10.xyzw
mov o1.w, l(1.000000)
dp4 o1.x, r1.xyzw, cb2[4].xyzw
dp4 o1.y, r1.xyzw, cb2[5].xyzw
dp4 o1.z, r1.xyzw, cb2[6].xyzw
mov r6.xyz, cb2[13].xyzx
mul r5.xyz, r4.yyyy, cb2[4].xyzx
div r5.xyz, r5.xyzx, cb2[30].xxxx
mad r6.xyz, r4.xxxx, r5.xyzx, r6.xyzx
add o3.xyz, r1.xyzx, -r6.xyzx
mov o2.w, v2.w
dp3 o4.y, r1.zxwz, cb0[3].xywx
dp3 o4.w, r1.zxwz, cb0[4].xywx
dp2 o4.x, r1.xzxx, cb0[3].xzxx
dp2 o4.z, r1.xzxx, cb0[4].xzxx
dp3 o5.w, r1.zxwz, cb0[2].xywx
dp3 o5.y, r1.zxwz, cb0[5].xywx
dp2 o5.z, r1.xzxx, cb0[2].xzxx
dp2 o5.x, r1.xzxx, cb0[5].xzxx
mul r0.xy, r1.xzxx, cb0[0].zzzz
mul r2.xyzw, cb0[1].zwzw, cb2[16].xxxx
mul r2.xyzw, r2.xyzw, l(0.021700, 0.021700, 0.041300, 0.041300)
mad o6.xy, r0.xyxx, l(0.430000, 0.430000, 0.000000, 0.000000), -r2.xyxx
mad o6.zw, r1.xxxz, cb0[0].zzzz, -r2.zzzw
mov o7.xy, r1.xzxx
mul r0.xy, v1.zxzz, v2.yzyy
mad r0.xy, v1.yzyy, v2.zxzz, -r0.xyxx
mul r0.zw, v2.zzzx, v3.yyyz
mad r0.zw, v2.yyyz, v3.zzzx, -r0.zzzw
mul r1.xy, r0.zwzz, v1.xyxx
add r1.x, r1.y, r1.x
mul r1.y, v2.y, v3.x
mad r1.y, v2.x, v3.y, -r1.y
mad r1.x, v1.z, r1.y, r1.x
div r1.x, l(1.000000, 1.000000, 1.000000, 1.000000), r1.x
mul r2.xw, r0.xxxy, r1.xxxx
mov r3.w, r2.x
mul r0.xy, v1.yzyy, v3.zxzz
mad r0.xy, v1.zxzz, v3.yzyy, -r0.xyxx
mul r2.xy, r0.xyxx, r1.xxxx
mov r3.z, r2.x
mul r3.xy, r0.zwzz, r1.xxxx
mov o8.xyz, r3.xzwx
mov r0.x, v1.w
mov r0.y, v2.w
mov r0.z, v3.w
dp3 r0.w, r3.xzwx, r0.xyzx
mov r2.z, r3.y
mov o8.w, -r0.w
dp3 r0.w, r2.zywz, r0.xyzx
mov o9.xyz, r2.zywz
mov o9.w, -r0.w
mul r2.x, r1.x, r1.y
mul r0.w, v1.x, v3.y
mad r0.w, v1.y, v3.x, -r0.w
mul r2.y, r0.w, r1.x
mul r0.w, v1.y, v2.x
mad r0.w, v1.x, v2.y, -r0.w
mul r2.z, r0.w, r1.x
dp3 r0.x, r2.xyzx, r0.xyzx
mov o10.xyz, r2.xyzx
mov o10.w, -r0.x
ret
// Approximately 0 instruction slots used
