// AUTOMATICALLY CONVERTED FROM SHADER FIXES 
//
// Generated by Microsoft (R) D3D Shader Disassembler
//
//   using 3Dmigoto v0.6.193 on Thu May 23 19:45:28 2024
//
//
// Note: shader requires additional functionality:
//       Early depth-stencil
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_Position              0   xyzw        0      POS   float   xyz
// TEXCOORD                 0   x           1     NONE    uint   x
// SV_IsFrontFace           0   x           2    FFACE    uint   x
//
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
ps_5_0
dcl_globalFlags refactoringAllowed | forceEarlyDepthStencil
dcl_constantbuffer CB0[9], immediateIndexed
dcl_constantbuffer CB7[28], immediateIndexed
dcl_resource_structured t1, 112
dcl_resource_texture2d (float,float,float,float) t3
dcl_uav_typed_buffer (uint,uint,uint,uint) u0
dcl_uav_typed_buffer (uint,uint,uint,uint) u1
dcl_input_ps_siv linear noperspective v0.xyz, position
dcl_input_ps constant v1.x
dcl_input_ps_sgv constant v2.x, is_front_face
dcl_temps 35
dcl_resource_buffer (float,float,float,float) t125
ld_indexable(buffer)(float,float,float,float) r25.xyzw, l(0, 0, 0, 0), t125.xyzw
dcl_resource_texture1d (float,float,float,float) t120
ld_indexable(texture1d)(float,float,float,float) r20.xyzw, l(4, 0, 0, 0), t120.xyzw
ftou r0.xy, v0.xyxx
mov r0.zw, l(0,0,0,0)
ld_indexable(texture2d)(float,float,float,float) r0.zw, r0.xyzw, t3.zwxy
utof r1.xy, r0.xyxx
mul r26.x, cb7[32].x, l(-0.062500)
mad r1.x, r25.x, r26.x, r1.x
mad r1.xzw, cb0[6].xxyz, r1.xxxx, cb0[8].xxyz
mad r1.xyz, cb0[7].xyzx, r1.yyyy, r1.xzwx
mul r2.xyz, r0.wwww, r1.xyzx
mul r27.x, r25.y, cb0[0].x
mul r27.y, r25.y, cb0[1].x
mul r27.z, r25.y, cb0[2].x
mul r27.w, cb0[0].x, cb0[0].x
mad r27.w, cb0[1].x, cb0[1].x, r27.w
mad r27.w, cb0[2].x, cb0[2].x, r27.w
div r27.xyz, r27.xyzx, r27.wwww
mov r28.xyz, cb0[5].xyzx
mad r28.xyz, r25.xxxx, r27.xyzx, r28.xyzx
ld_structured_indexable(structured_buffer, stride=112)(mixed,mixed,mixed,mixed) r3.xyzw, v1.x, l(48), t1.xyzw
ld_structured_indexable(structured_buffer, stride=112)(mixed,mixed,mixed,mixed) r4.xyzw, v1.x, l(64), t1.xyzw
ld_structured_indexable(structured_buffer, stride=112)(mixed,mixed,mixed,mixed) r5.xyzw, v1.x, l(80), t1.xyzw
ld_structured_indexable(structured_buffer, stride=112)(mixed,mixed,mixed,mixed) r6.xyzw, v1.x, l(96), t1.xyzw
ftou r3.xw, r3.xxxw
imad r0.x, r0.y, cb0[5].w, r0.x
ishl r0.x, r0.x, l(3)
ieq r0.y, r3.x, l(3)
if_nz r0.y
  mov r7.x, r4.w
  mov r7.y, r5.w
  mov r7.z, r6.w
  add r7.xyz, r7.xyzx, -r28.xyzx
  mad r8.xyz, -r1.xyzx, r0.wwww, r7.xyzx
  dp3 r9.x, r4.xyzx, r8.xyzx
  dp3 r9.y, r5.xyzx, r8.xyzx
  dp3 r9.z, r6.xyzx, r8.xyzx
  mad r7.xyz, -r1.xyzx, r0.zzzz, r7.xyzx
  dp3 r8.x, r4.xyzx, r7.xyzx
  dp3 r8.y, r5.xyzx, r7.xyzx
  dp3 r8.z, r6.xyzx, r7.xyzx
  add r7.xyz, -r9.xyzx, r8.xyzx
  dp3 r0.y, r7.xyzx, r7.xyzx
  rsq r1.w, r0.y
  mul r7.xyz, r1.wwww, r7.xyzx
  max r1.w, |r9.y|, |r9.x|
  max r1.w, |r9.z|, r1.w
  ge r1.w, l(1.000000), r1.w
  rcp r8.xyz, r7.xyzx
  add r10.xyz, -r9.xyzx, l(-1.000000, -1.000000, -1.000000, 0.000000)
  mul r10.xyz, r8.xyzx, r10.xyzx
  add r9.xyz, -r9.xyzx, l(1.000000, 1.000000, 1.000000, 0.000000)
  mul r8.xyz, r8.xyzx, r9.xyzx
  min r9.xyz, r8.xyzx, r10.xyzx
  max r8.xyz, r8.xyzx, r10.xyzx
  max r2.w, r9.y, r9.x
  max r2.w, r9.z, r2.w
  min r5.w, r8.y, r8.x
  min r5.w, r8.z, r5.w
  ge r5.w, r5.w, r2.w
  lt r6.w, l(0.000000), r2.w
  and r5.w, r5.w, r6.w
  mul r7.xyz, r2.wwww, r7.xyzx
  dp3 r2.w, r7.xyzx, r7.xyzx
  sqrt r2.w, r2.w
  sqrt r0.y, r0.y
  ge r0.y, r0.y, r2.w
  or r0.y, r1.w, r0.y
  movc r0.y, r5.w, r0.y, r1.w
else
  ieq r1.w, r3.x, l(2)
  if_nz r1.w
    mul r7.xyz, r5.zxyz, r6.yzxy
    mad r7.xyz, r5.yzxy, r6.zxyz, -r7.xyzx
    mul r8.xyz, r3.yyyy, r5.xyzx
    mad r9.xyz, r6.xyzx, r3.zzzz, -r8.xyzx
    mad r6.xyz, -r6.xyzx, r3.zzzz, -r8.xyzx
    mad r10.xyz, r7.xyzx, r3.zzzz, -r8.xyzx
    mad r3.xyz, -r7.xyzx, r3.zzzz, -r8.xyzx
    add r7.xyz, r4.xyzx, -r28.xyzx
    mad r8.xyz, r1.xyzx, r0.wwww, -r7.xyzx
    dp3 r1.w, -r5.xyzx, r8.xyzx
    ge r1.w, r1.w, l(0.000000)
    mad r11.xyz, r1.xyzx, r0.zzzz, -r7.xyzx
    dp3 r2.w, -r5.xyzx, r11.xyzx
    ge r2.w, r2.w, l(0.000000)
    or r1.w, r1.w, r2.w
    dp3 r2.w, r9.xyzx, r8.xyzx
    lt r2.w, r2.w, l(0.000000)
    dp3 r5.w, r9.xyzx, r11.xyzx
    lt r5.w, r5.w, l(0.000000)
    and r2.w, r2.w, r5.w
    dp3 r5.w, r6.xyzx, r8.xyzx
    lt r5.w, r5.w, l(0.000000)
    dp3 r6.x, r6.xyzx, r11.xyzx
    lt r6.x, r6.x, l(0.000000)
    and r5.w, r5.w, r6.x
    or r2.w, r2.w, r5.w
    dp3 r5.w, r10.xyzx, r8.xyzx
    lt r5.w, r5.w, l(0.000000)
    dp3 r6.x, r10.xyzx, r11.xyzx
    lt r6.x, r6.x, l(0.000000)
    and r5.w, r5.w, r6.x
    or r2.w, r2.w, r5.w
    dp3 r5.w, r3.xyzx, r8.xyzx
    lt r5.w, r5.w, l(0.000000)
    dp3 r3.x, r3.xyzx, r11.xyzx
    lt r3.x, r3.x, l(0.000000)
    and r3.x, r3.x, r5.w
    or r2.w, r2.w, r3.x
    mad r3.xyz, -r5.xyzx, r4.wwww, r7.xyzx
    mad r6.xyz, r1.xyzx, r0.wwww, -r3.xyzx
    dp3 r5.w, r5.xyzx, r6.xyzx
    lt r5.w, r5.w, l(0.000000)
    mad r3.xyz, r1.xyzx, r0.zzzz, -r3.xyzx
    dp3 r3.x, r5.xyzx, r3.xyzx
    lt r3.x, r3.x, l(0.000000)
    and r3.x, r3.x, r5.w
    or r2.w, r2.w, r3.x
    movc r0.y, r2.w, l(0), r1.w
  else
    mad r2.xyz, r1.xyzx, r0.zzzz, -r2.xyzx
    dp3 r0.z, r2.xyzx, r2.xyzx
    rsq r1.w, r0.z
    mul r2.xyz, r1.wwww, r2.xyzx
    add r3.xyz, r4.xyzx, -r28.xyzx
    mad r4.xyz, r1.xyzx, r0.wwww, -r3.xyzx
    dp3 r1.w, r4.xyzx, r4.xyzx
    sqrt r1.w, r1.w
    ge r1.w, r4.w, r1.w
    mad r1.xyz, -r1.xyzx, r0.wwww, r3.xyzx
    dp3 r2.w, r1.xyzx, r2.xyzx
    mul r3.x, r4.w, r4.w
    mad r3.x, r2.w, r2.w, r3.x
    dp3 r1.x, r1.xyzx, r1.xyzx
    add r1.x, -r1.x, r3.x
    lt r1.y, l(0.000000), r1.x
    lt r1.z, l(0.000000), r2.w
    and r1.y, r1.z, r1.y
    sqrt r1.x, r1.x
    add r1.x, -r1.x, r2.w
    mul r2.xyz, r1.xxxx, r2.xyzx
    dp3 r1.x, r2.xyzx, r2.xyzx
    sqrt r1.x, r1.x
    sqrt r0.z, r0.z
    ge r0.z, r0.z, r1.x
    or r0.z, r1.w, r0.z
    movc r0.y, r1.y, r0.z, r1.w
  endif
endif
ushr r0.z, r3.w, l(5)
iadd r0.x, r0.z, r0.x
ishl r0.z, l(1), r3.w
atomic_or u1, r0.x, r0.z
if_nz r0.y
  add r0.y, v0.z, -cb0[4].x
  div r0.y, cb0[4].y, r0.y
  ge r0.y, r0.y, r0.w
  or r0.y, r0.y, v2.x
  if_nz r0.y
    atomic_or u0, r0.x, r0.z
  endif
endif
ret
// Approximately 0 instruction slots used
