// AUTOMATICALLY CONVERTED FROM SHADER FIXES 
//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//   using 3Dmigoto v0.6.89 on Wed Dec 21 16:56:41 2022
//
//
// Buffer Definitions:
//
// cbuffer cb2
// {
//
//   float4 cb2[10];                    // Index:    0-9              Components:    40
//
// }
//
// cbuffer cb1
// {
//
//   float4 cb1[4];                     // Index:    0 1 2 3          Components:    16
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// StereoParams                      texture  float4          2d  125        1
// cb1                               cbuffer      NA          NA    1        1
// cb2                               cbuffer      NA          NA    2        1
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION                 0   xyz         0     NONE   float   xyz
// TEXCOORD                 0   xy          1     NONE   float   xy
// NORMAL                   0   xyz         2     NONE   float
// TANGENT                  0   xyzw        3     NONE   float
// COLOR                    0   xyzw        4     NONE   float   xyzw
// TEXCOORD                 1   xy          5     NONE   float
// INSTANCE_TRANSFORM       0   xyzw        6     NONE   float   xyzw
// INSTANCE_TRANSFORM       1   xyzw        7     NONE   float   xyzw
// INSTANCE_TRANSFORM       2   xyzw        8     NONE   float   xyzw
// INSTANCE_LOD_PARAMS      0   xyzw        9     NONE   float
// SV_InstanceID            0   x          10   INSTID    uint
//
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// TEXCOORD                 0   xyzw        0     NONE   float   xy
// TEXCOORD                 1   xyzw        1     NONE   float   xyzw
// TEXCOORD                 2   xyzw        2     NONE   float   xyzw
// TEXCOORD                 3   xyzw        3     NONE   float   xyzw
// SV_Position              0   xyzw        4      POS   float   xyzw
// P                        0   x           5  RTINDEX    uint   x
//
vs_5_0
dcl_output_siv o5.x, rendertarget_array_index
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB2[10], immediateIndexed
dcl_constantbuffer CB1[4], immediateIndexed
dcl_resource_buffer (float,float,float,float) t125
dcl_input v0.xyz
dcl_input v1.xy
dcl_input v4.xyzw
dcl_input v6.xyzw
dcl_input v7.xyzw
dcl_input v8.xyzw
dcl_output o0.xy
dcl_output o1.xyzw
dcl_output o2.xyzw
dcl_output o3.xyzw
dcl_output_siv o4.xyzw, position
dcl_temps 6
ld_indexable(buffer)(float,float,float,float) r5.xyzw, l(0, 0, 0, 0), t125.xyzw
mov o5.x, r5.z
mov o0.xy, v1.xyxx
mov o1.xyzw, v4.xyzw
mul r0.xyzw, v7.xyzw, cb1[0].yyyy
mad r0.xyzw, v6.xyzw, cb1[0].xxxx, r0.xyzw
mad r0.xyzw, v8.xyzw, cb1[0].zzzz, r0.xyzw
mad r0.xyzw, cb1[0].wwww, l(0.000000, 0.000000, 0.000000, 1.000000), r0.xyzw
mad r1.xyz, v0.xyzx, cb2[8].xyzx, cb2[9].xyzx
mov r1.w, l(1.000000)
dp4 r0.x, r1.xyzw, r0.xyzw
mul r2.xyzw, v7.xyzw, cb1[1].yyyy
mad r2.xyzw, v6.xyzw, cb1[1].xxxx, r2.xyzw
mad r2.xyzw, v8.xyzw, cb1[1].zzzz, r2.xyzw
mad r2.xyzw, cb1[1].wwww, l(0.000000, 0.000000, 0.000000, 1.000000), r2.xyzw
dp4 r0.y, r1.xyzw, r2.xyzw
mul r2.xyzw, v7.xyzw, cb1[2].yyyy
mad r2.xyzw, v6.xyzw, cb1[2].xxxx, r2.xyzw
mad r2.xyzw, v8.xyzw, cb1[2].zzzz, r2.xyzw
mad r2.xyzw, cb1[2].wwww, l(0.000000, 0.000000, 0.000000, 1.000000), r2.xyzw
dp4 r0.z, r1.xyzw, r2.xyzw
mul r2.xyzw, v7.xyzw, cb1[3].yyyy
mad r2.xyzw, v6.xyzw, cb1[3].xxxx, r2.xyzw
mad r2.xyzw, v8.xyzw, cb1[3].zzzz, r2.xyzw
mad r2.xyzw, cb1[3].wwww, l(0.000000, 0.000000, 0.000000, 1.000000), r2.xyzw
dp4 r0.w, r1.xyzw, r2.xyzw
mov o2.xyzw, r0.xyzw
mov r3.yzw, r0.yyzw
mov o3.xyzw, l(0,0,0,0)
ld_indexable(buffer)(float,float,float,float) r0.yz, l(0, 0, 0, 0), t125.zxyw
add r0.z, -r0.z, r0.w
mad r3.x, r0.y, r0.z, r0.x
add r4.x, -r5.y, r3.w
mul r4.y, r5.x, r5.w
mad r4.x, r4.x, r4.y, r3.x
ne r4.y, l(1.000000), r3.w
movc r3.x, r4.y, r4.x, r3.x
mov o4.xyzw, r3.xyzw
ret
// Approximately 31 instruction slots used
