// AUTOMATICALLY CONVERTED FROM SHADER FIXES 
//
// Generated by Microsoft (R) D3D Shader Disassembler
//
//   using 3Dmigoto v0.6.63 on Sun Oct  9 13:49:06 2022
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION                 0   xyzw        0     NONE   float   xyz
// TEXCOORD                 0   xy          1     NONE   float   xy
// TEXCOORD                 1   xy          2     NONE   float   xy
// NORMAL                   0   xyz         3     NONE   float   xyz
// TANGENT                  0   xyzw        4     NONE   float
// SV_InstanceID            0   x           5   INSTID    uint   x
// SV_VertexID              0   x           6   VERTID    uint   x
//
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_POSITION              0   xyzw        0      POS   float   xyzw
// VERT_ID                  0   x           1     NONE    uint   x
// TEXCOORD                 0   xy          2     NONE   float   xy
// TEXCOORD                 1   xy          3     NONE   float   xy
// NORMAL                   0   xyz         4     NONE   float   xyz
// TEXCOORD                 7   xyz         5     NONE   float   xyz
// P                        0   x           6  RTINDEX    uint   x
//
vs_5_0
dcl_output_siv o6.x, rendertarget_array_index
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB1[6], immediateIndexed
dcl_constantbuffer CB2[37], immediateIndexed
dcl_resource_structured t2, 104
dcl_input v0.xyz
dcl_input v1.xy
dcl_input v2.xy
dcl_input v3.xyz
dcl_input_sgv v5.x, instance_id
dcl_input_sgv v6.x, vertex_id
dcl_output_siv o0.xyzw, position
dcl_output o1.x
dcl_output o2.xy
dcl_output o3.xy
dcl_output o4.xyz
dcl_output o5.xyz
dcl_temps 53
dcl_resource_buffer (float,float,float,float) t125
ld_indexable(buffer)(float,float,float,float) r52.xyzw, l(0, 0, 0, 0), t125.xyzw
mov o6.x, r52.z
ld_indexable(buffer)(float,float,float,float) r40.xyzw, l(0, 0, 0, 0), t125.xyzw
iadd r0.x, v5.x, cb1[1].y
ld_structured_indexable(structured_buffer, stride=104)(mixed,mixed,mixed,mixed) r1.xyzw, r0.x, l(0), t2.xyzw
mov r2.x, r1.w
ld_structured_indexable(structured_buffer, stride=104)(mixed,mixed,mixed,mixed) r3.xyzw, r0.x, l(16), t2.xyzw
mov r2.y, r3.w
ld_structured_indexable(structured_buffer, stride=104)(mixed,mixed,mixed,mixed) r4.xyzw, r0.x, l(32), t2.xyzw
ld_structured_indexable(structured_buffer, stride=104)(mixed,mixed,mixed,mixed) r0.x, r0.x, l(100), t2.xxxx
bfi o1.x, l(24), l(0), v6.x, r0.x
mov r2.z, r4.w
mad r0.xyz, v0.xyzx, cb1[4].xyzx, cb1[5].xyzx
dp3 r5.x, r0.xyzx, r1.xyzx
dp3 r5.y, r0.xyzx, r3.xyzx
dp3 r5.z, r0.xyzx, r4.xyzx
add r0.xyz, r2.xyzx, r5.xyzx
add r2.xyz, r0.xyzx, -cb2[31].xyzx
dp3 r0.w, r2.xyzx, r2.xyzx
rsq r0.w, r0.w
mul r2.xyz, r0.wwww, r2.xyzx
mad r5.xyz, v3.xyzx, l(2.000000, 2.000000, 2.000000, 0.000000), l(-1.000000, -1.000000, -1.000000, 0.000000)
dp3 r1.x, r5.xyzx, r1.xyzx
dp3 r1.y, r5.xyzx, r3.xyzx
dp3 r1.z, r5.xyzx, r4.xyzx
dp3 r0.w, r1.xyzx, r1.xyzx
rsq r0.w, r0.w
mul r1.xyz, r0.wwww, r1.xyzx
dp3_sat r0.w, -r2.xyzx, r1.xyzx
add r0.w, -r0.w, l(1.000000)
mul r3.xyz, r1.xyzx, cb2[36].yyyy
mov o4.xyz, r1.xyzx
mad r1.xyz, -r3.xyzx, r0.wwww, r0.xyzx
mad r2.xyz, r2.xyzx, cb2[30].wwww, r1.xyzx
add r1.xyz, r1.xyzx, cb2[30].xyzx
ieq r0.w, l(1), cb2[36].x
movc r1.xyz, r0.wwww, r1.xyzx, r2.xyzx
movc r0.xyz, cb2[36].xxxx, r1.xyzx, r0.xyzx
mov r0.w, l(1.000000)
dp4 r42.x, r0.xyzw, cb2[16].xyzw
dp4 r42.y, r0.xyzw, cb2[17].xyzw
dp4 r42.z, r0.xyzw, cb2[18].xyzw
dp4 r42.w, r0.xyzw, cb2[19].xyzw
ieq r41.x, r42.w, l(0x3f800000)
ieq r41.y, l(1), cb2[36].x
if_nz r41.x
  if_z r41.y
    add r40.w, r42.w, -r40.y
    mad r42.x, r40.x, r40.w, r42.x
  endif
endif
mov r50.xyzw, r42.xyzw
mov o5.xyz, r0.xyzx
mov o2.xy, v1.xyxx
mov o3.xy, v2.xyxx
add r51.x, -r52.y, r50.w
mul r51.y, r52.x, r52.w
mad r51.x, r51.x, r51.y, r50.x
ne r51.y, l(1.000000), r50.w
movc r50.x, r51.y, r51.x, r50.x
mov o0.xyzw, r50.xyzw
ret
// Approximately 0 instruction slots used
