// AUTOMATICALLY CONVERTED FROM SHADER FIXES 
//
// Generated by Microsoft (R) D3D Shader Disassembler
//
//   using 3Dmigoto v0.6.63 on Sun Oct  9 13:49:37 2022
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION                 0   xyzw        0     NONE   float   xyz
// TEXCOORD                 0   xy          1     NONE   float   xy
// NORMAL                   0   xyz         2     NONE   float   xyz
// TANGENT                  0   xyzw        3     NONE   float   xyzw
// TEXCOORD                 5   xyz         4     NONE   float   xyz
// TEXCOORD                 7   xyzw        5     NONE   float
// SV_InstanceID            0   x           6   INSTID    uint   x
// SV_VertexID              0   x           7   VERTID    uint   x
//
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_POSITION              0   xyzw        0      POS   float   xyzw
// VERT_ID                  0   x           1     NONE    uint   x
// TEXCOORD                 0   xy          2     NONE   float   xy
// NORMAL                   0   xyz         3     NONE   float   xyz
// TANGENT                  0   xyz         4     NONE   float   xyz
// BINORMAL                 0   xyz         5     NONE   float   xyz
// TEXCOORD                 7   xyz         6     NONE   float   xyz
// P                        0   x           7  RTINDEX    uint   x
//
vs_5_0
dcl_output_siv o7.x, rendertarget_array_index
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB1[6], immediateIndexed
dcl_constantbuffer CB3[20], immediateIndexed
dcl_resource_structured t3, 104
dcl_input v0.xyz
dcl_input v1.xy
dcl_input v2.xyz
dcl_input v3.xyzw
dcl_input v4.xyz
dcl_input_sgv v6.x, instance_id
dcl_input_sgv v7.x, vertex_id
dcl_output_siv o0.xyzw, position
dcl_output o1.x
dcl_output o2.xy
dcl_output o3.xyz
dcl_output o4.xyz
dcl_output o5.xyz
dcl_output o6.xyz
dcl_temps 53
dcl_resource_buffer (float,float,float,float) t125
ld_indexable(buffer)(float,float,float,float) r52.xyzw, l(0, 0, 0, 0), t125.xyzw
mov o7.x, r52.z
ld_indexable(buffer)(float,float,float,float) r40.xyzw, l(0, 0, 0, 0), t125.xyzw
mad r0.xyz, v0.xyzx, cb1[4].xyzx, cb1[5].xyzx
iadd r0.w, v6.x, cb1[1].y
ld_structured_indexable(structured_buffer, stride=104)(mixed,mixed,mixed,mixed) r1.x, r0.w, l(100), t3.xxxx
ubfe r1.y, l(8), l(16), r1.x
bfi o1.x, l(24), l(0), v7.x, r1.x
utof r1.x, r1.y
mul r1.x, r1.x, l(0.00392156886)
mad r0.xyz, -v4.xyzx, r1.xxxx, r0.xyzx
ld_structured_indexable(structured_buffer, stride=104)(mixed,mixed,mixed,mixed) r1.xyzw, r0.w, l(0), t3.xyzw
dp3 r2.x, r0.xyzx, r1.xyzx
ld_structured_indexable(structured_buffer, stride=104)(mixed,mixed,mixed,mixed) r3.xyzw, r0.w, l(16), t3.xyzw
ld_structured_indexable(structured_buffer, stride=104)(mixed,mixed,mixed,mixed) r4.xyzw, r0.w, l(32), t3.xyzw
dp3 r2.y, r0.xyzx, r3.xyzx
dp3 r2.z, r0.xyzx, r4.xyzx
mov r0.x, r1.w
mov r0.y, r3.w
mov r0.z, r4.w
add r0.xyz, r0.xyzx, r2.xyzx
mov r0.w, l(1.000000)
dp4 r42.x, r0.xyzw, cb3[16].xyzw
dp4 r42.y, r0.xyzw, cb3[17].xyzw
dp4 r42.z, r0.xyzw, cb3[18].xyzw
dp4 r42.w, r0.xyzw, cb3[19].xyzw
ieq r41.x, r42.w, l(0x3f800000)
if_nz r41.x
  add r40.w, r42.w, -r40.y
  mad r42.x, r40.x, r40.w, r42.x
endif
mov r50.xyzw, r42.xyzw
mov o6.xyz, r0.xyzx
mov o2.xy, v1.xyxx
mad r0.xyz, v2.xyzx, l(2.000000, 2.000000, 2.000000, 0.000000), l(-1.000000, -1.000000, -1.000000, 0.000000)
dp3 r2.x, r0.xyzx, r1.xyzx
dp3 r2.y, r0.xyzx, r3.xyzx
dp3 r2.z, r0.xyzx, r4.xyzx
dp3 r0.x, r2.xyzx, r2.xyzx
rsq r0.x, r0.x
mul r0.xyz, r0.xxxx, r2.xyzx
mov o3.xyz, r0.xyzx
mad r2.xyzw, v3.xyzw, l(2.000000, 2.000000, 2.000000, 2.000000), l(-1.000000, -1.000000, -1.000000, -1.000000)
dp3 r1.x, r2.xyzx, r1.xyzx
dp3 r1.y, r2.xyzx, r3.xyzx
dp3 r1.z, r2.xyzx, r4.xyzx
dp3 r0.w, r1.xyzx, r1.xyzx
rsq r0.w, r0.w
mul r1.xyz, r0.wwww, r1.xyzx
mov o4.xyz, r1.xyzx
mul r2.xyz, r0.zxyz, r1.yzxy
mad r0.xyz, r0.yzxy, r1.zxyz, -r2.xyzx
mul r0.xyz, r2.wwww, r0.xyzx
dp3 r0.w, r0.xyzx, r0.xyzx
rsq r0.w, r0.w
mul r0.xyz, r0.wwww, r0.xyzx
and r0.w, l(16), cb1[0].y
movc r0.w, r0.w, l(-1.000000), l(1.000000)
mul o5.xyz, r0.xyzx, r0.wwww
add r51.x, -r52.y, r50.w
mul r51.y, r52.x, r52.w
mad r51.x, r51.x, r51.y, r50.x
ne r51.y, l(1.000000), r50.w
movc r50.x, r51.y, r51.x, r50.x
mov o0.xyzw, r50.xyzw
ret
// Approximately 0 instruction slots used
