// AUTOMATICALLY CONVERTED FROM SHADER FIXES 
//
// Generated by Microsoft (R) D3D Shader Disassembler
//
//   using 3Dmigoto v0.6.123 on Fri Mar  3 16:59:07 2023
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_0
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[5], immediateIndexed
dcl_constantbuffer CB1[126], immediateIndexed
dcl_resource_texture2d (float,float,float,float) t0
dcl_resource_texture2d (float,float,float,float) t1
dcl_uav_typed_texture2darray (float,float,float,float) u0
dcl_uav_typed_texture2darray (float,float,float,float) u1
dcl_input vThreadIDInGroupFlattened
dcl_input vThreadGroupID.xy
dcl_input vThreadID.xy
dcl_temps 32
dcl_constantbuffer CB14[2], immediateIndexed
dcl_tgsm_structured g0, 16, 256
dcl_thread_group 16, 16, 1
mov r32.z, l(0)
iadd r0.xy, vThreadID.xyxx, cb0[3].xyxx
iadd r0.zw, cb0[3].zzzw, l(0, 0, -1, -1)
umin r0.xy, r0.zwzz, r0.xyxx
mov r0.zw, l(0,0,0,0)
ld_indexable(texture2d)(float,float,float,float) r1.xy, r0.xyww, t0.xyzw
ld_indexable(texture2d)(float,float,float,float) r0.z, r0.xyzw, t1.yzxw
lt r0.w, l(0.000000), r1.x
mad r1.xy, r1.xyxx, l(4.008016, 4.008016, 0.000000, 0.000000), l(-2.00397754, -2.00397754, 0.000000, 0.000000)
utof r1.zw, vThreadID.xxxy
add r1.zw, r1.zzzw, l(0.000000, 0.000000, 0.500000, 0.500000)
div r2.xy, r1.zwzz, cb0[4].xyxx
add r2.z, -r2.y, l(1.000000)
mad r1.zw, r2.xxxz, l(0.000000, 0.000000, 2.000000, 2.000000), l(0.000000, 0.000000, -1.000000, -1.000000)
ge r27.x, cb14[0].x, l(5.000000)
mov r21.z, r1.z
mul r25.w, cb14[0].y, r0.z
mul r25.w, r25.w, l(-0.100000)
add r25.w, r25.w, l(1.000000)
mad r21.z, -cb14[0].x, r25.w, r21.z
mul r2.xyz, r1.wwww, cb1[123].xywx
mad r2.xyz, r21.zzzz, cb1[122].xywx, r2.xyzx
mad r2.xyz, r0.zzzz, cb1[124].xywx, r2.xyzx
add r2.xyz, r2.xyzx, cb1[125].xywx
if_z r27.x
  mul r25.w, cb14[2].y, r0.z
  mul r25.w, r25.w, l(-0.100000)
  add r25.w, r2.z, r25.w
  mad r2.x, cb14[2].x, r25.w, r2.x
else
  mul r25.w, cb14[0].y, r0.z
  mul r25.w, r25.w, l(-0.100000)
  add r25.w, r2.z, r25.w
  mad r2.x, cb14[0].x, r25.w, r2.x
endif
div r2.xy, r2.xyxx, r2.zzzz
add r1.zw, r1.zzzw, -r2.xxxy
movc r1.xy, r0.wwww, r1.xyxx, r1.zwzz
mul r1.z, r1.y, -cb0[0].x
dp2 r0.w, r1.xzxx, r1.xzxx
sqrt r2.x, r0.w
max r0.w, |r1.z|, |r1.x|
min r1.y, |r1.z|, |r1.x|
div r0.w, r1.y, r0.w
mul r1.y, r0.w, r0.w
mad r1.w, r1.y, l(0.0872929022), l(-0.301895)
mad r1.y, r1.w, r1.y, l(1.000000)
mul r1.w, r0.w, r1.y
lt r2.z, |r1.x|, |r1.z|
mad r0.w, -r1.y, r0.w, l(1.57079637)
movc r0.w, r2.z, r0.w, r1.w
lt r1.xy, r1.xzxx, l(0.000000, 0.000000, 0.000000, 0.000000)
add r1.z, -r0.w, l(3.14159274)
movc r0.w, r1.x, r1.z, r0.w
movc r2.y, r1.y, -r0.w, r0.w
ne r1.xy, r2.xyxx, r2.xyxx
or r0.w, r1.y, r1.x
movc r1.xy, r0.wwww, l(0,0,0,0), r2.xyxx
ult r2.xy, r0.xyxx, cb0[3].zwzz
and r0.w, r2.y, r2.x
if_nz r0.w
  mad r2.x, r0.z, cb1[65].x, cb1[65].y
  mad r0.z, r0.z, cb1[65].z, -cb1[65].w
  div r0.z, l(1.000000, 1.000000, 1.000000, 1.000000), r0.z
  add r1.z, r0.z, r2.x
  mad r1.w, r1.y, l(0.159154937), l(0.500000)
  mov r32.xy, r0.xyyy
  store_uav_typed u0.xyzw, r32.xyzz, r1.xwzz
endif
div r0.x, cb0[0].w, cb0[0].y
min r0.x, r0.x, r1.x
movc r2.x, r0.w, r0.x, l(2.000000)
and r2.z, r0.x, r0.w
mov r2.yw, r1.yyyy
store_structured g0.xyzw, vThreadIDInGroupFlattened.x, l(0), r2.xyzw
sync_g_t
ult r0.xyzw, vThreadIDInGroupFlattened.xxxx, l(128, 64, 32, 16)
if_nz r0.x
  iadd r0.x, vThreadIDInGroupFlattened.x, l(128)
  ld_structured r1.xyzw, r0.x, l(0), g0.xyzw
  lt r0.x, r2.x, r1.x
  movc r3.xy, r0.xxxx, r2.xwxx, r1.xyxx
  lt r0.x, r1.z, r2.z
  movc r3.zw, r0.xxxx, r2.zzzw, r1.zzzw
  store_structured g0.xyzw, vThreadIDInGroupFlattened.x, l(0), r3.xyzw
endif
sync_g_t
if_nz r0.y
  ld_structured r1.xyzw, vThreadIDInGroupFlattened.x, l(0), g0.xyzw
  iadd r0.x, vThreadIDInGroupFlattened.x, l(64)
  ld_structured r2.xyzw, r0.x, l(0), g0.xyzw
  lt r0.x, r1.x, r2.x
  movc r3.xy, r0.xxxx, r1.xyxx, r2.xyxx
  lt r0.x, r2.z, r1.z
  movc r3.zw, r0.xxxx, r1.zzzw, r2.zzzw
  store_structured g0.xyzw, vThreadIDInGroupFlattened.x, l(0), r3.xyzw
endif
sync_g_t
if_nz r0.z
  ld_structured r1.xyzw, vThreadIDInGroupFlattened.x, l(0), g0.xyzw
  iadd r0.x, vThreadIDInGroupFlattened.x, l(32)
  ld_structured r2.xyzw, r0.x, l(0), g0.xyzw
  lt r0.x, r1.x, r2.x
  movc r3.xy, r0.xxxx, r1.xyxx, r2.xyxx
  lt r0.x, r2.z, r1.z
  movc r3.zw, r0.xxxx, r1.zzzw, r2.zzzw
  store_structured g0.xyzw, vThreadIDInGroupFlattened.x, l(0), r3.xyzw
endif
if_nz r0.w
  ld_structured r0.xyzw, vThreadIDInGroupFlattened.x, l(0), g0.xyzw
  iadd r1.x, vThreadIDInGroupFlattened.x, l(16)
  ld_structured r1.xyzw, r1.x, l(0), g0.xyzw
  lt r2.x, r0.x, r1.x
  movc r2.xy, r2.xxxx, r0.xyxx, r1.xyxx
  lt r0.x, r1.z, r0.z
  movc r2.zw, r0.xxxx, r0.zzzw, r1.zzzw
  store_structured g0.xyzw, vThreadIDInGroupFlattened.x, l(0), r2.xyzw
endif
ult r0.xyzw, vThreadIDInGroupFlattened.xxxx, l(8, 4, 2, 1)
if_nz r0.x
  ld_structured r1.xyzw, vThreadIDInGroupFlattened.x, l(0), g0.xyzw
  iadd r0.x, vThreadIDInGroupFlattened.x, l(8)
  ld_structured r2.xyzw, r0.x, l(0), g0.xyzw
  lt r0.x, r1.x, r2.x
  movc r3.xy, r0.xxxx, r1.xyxx, r2.xyxx
  lt r0.x, r2.z, r1.z
  movc r3.zw, r0.xxxx, r1.zzzw, r2.zzzw
  store_structured g0.xyzw, vThreadIDInGroupFlattened.x, l(0), r3.xyzw
endif
if_nz r0.y
  ld_structured r1.xyzw, vThreadIDInGroupFlattened.x, l(0), g0.xyzw
  iadd r0.x, vThreadIDInGroupFlattened.x, l(4)
  ld_structured r2.xyzw, r0.x, l(0), g0.xyzw
  lt r0.x, r1.x, r2.x
  movc r3.xy, r0.xxxx, r1.xyxx, r2.xyxx
  lt r0.x, r2.z, r1.z
  movc r3.zw, r0.xxxx, r1.zzzw, r2.zzzw
  store_structured g0.xyzw, vThreadIDInGroupFlattened.x, l(0), r3.xyzw
endif
if_nz r0.z
  ld_structured r1.xyzw, vThreadIDInGroupFlattened.x, l(0), g0.xyzw
  iadd r0.x, vThreadIDInGroupFlattened.x, l(2)
  ld_structured r2.xyzw, r0.x, l(0), g0.xyzw
  lt r0.x, r1.x, r2.x
  movc r3.xy, r0.xxxx, r1.xyxx, r2.xyxx
  lt r0.x, r2.z, r1.z
  movc r3.zw, r0.xxxx, r1.zzzw, r2.zzzw
  store_structured g0.xyzw, vThreadIDInGroupFlattened.x, l(0), r3.xyzw
endif
if_nz r0.w
  ld_structured r0.xyzw, l(0), l(0), g0.xyzw
  ld_structured r1.xyzw, l(1), l(0), g0.xyzw
  lt r2.x, r0.x, r1.x
  movc r2.xy, r2.xxxx, r0.xyxx, r1.xyxx
  lt r0.x, r1.z, r0.z
  movc r2.zw, r0.xxxx, r0.zzzw, r1.zzzw
  store_structured g0.xyzw, l(0), l(0), r2.xyzw
endif
if_z vThreadIDInGroupFlattened.x
  ld_structured r0.xyzw, l(0), l(0), g0.xyzw
  sincos r1.x, r2.x, r0.y
  mov r2.y, r1.x
  mul r1.xy, r0.xxxx, r2.xyxx
  sincos r0.x, r2.x, r0.w
  mov r2.z, r2.x
  mov r2.w, r0.x
  mul r1.zw, r0.zzzz, r2.zzzw
  mov r32.xy, vThreadGroupID.xyyy
  store_uav_typed u1.xyzw, r32.xyzz, r1.xyzw
endif
ret
// Approximately 0 instruction slots used
